1. Field
The following description relates to a method for compensating for a sampling clock-offset in wireless communications. The following description also relates to an apparatus for compensating for a sampling clock-offset in wireless communications.
2. Description of Related Art
In a digital communication receiver, a mismatch between a desired sampling time and an actual sampling time may occur. Such a mismatch may occur due to a jitter that may occur in a clock feeding performed by an analog-to-digital converter (ADC), and such a mismatch may result in error samples in the demodulation of data symbols.
A sampling clock-offset may cause samples of a symbol to overlap a subsequent symbol or a previous symbol depending on a sign of a clock-offset. Thus, demodulation of a symbol may result in an erroneous decision about a demodulated symbol due to the presence of samples of adjacent symbols. During the demodulation of a symbol, a sampling clock-offset may be accumulated when a data length increases. Such a phenomenon may not be overcome simply by increasing a signal-to-noise ratio (SNR).